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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg714/adg715 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., cmos, low voltage serially controlled, octal spst switches functional block diagrams adg714 d1 d2 d3 d4 d5 d6 d7 d8 dout s1 s2 s3 s4 s5 s6 s7 s8 input shift register sclk din sync reset adg715 d1 d2 d3 d4 d5 d6 d7 d8 s1 s2 s3 s4 s5 s6 s7 s8 interface logic sda scl a0 a1 reset features adg714 spi?/qspi?/microwire?-compatible interface adg715 i 2 c?-compatible interface 2.7 v to 5.5 v single supply 2.5 v dual supply 2.5 on resistance 0.6 on resistance flatness 100 pa leakage currents octal spst power-on reset fast switching times ttl/cmos-compatible small tssop package applications data acquisition systems communication systems relay replacement audio and video switching general description the adg714/adg715 are cmos, octal spst (single-pole, single-throw) switches controlled via either a 2- or 3-wire se rial interface. on resistance is closely matched between switches and very flat over the full signal range. each switch conducts equally well in both directions and the input signal range extends to the supplies. data is written to these devices in the form of 8 bits, each bit corresponding to one channel. the adg714 uses a 3-wire serial interface that is compatible with spi , qspi, and microwire and most dsp interface standards. the output of the shift register dout enables a number of these parts to be daisy chained. the adg715 uses a 2-wire serial interface that is compatible with the i 2 c interface standard. the adg715 has four hard wired addresses, selectable from two external address pins (a0 and a1). this allows the 2 lsbs of the 7-bit slave address to be set by the user. a maximum of four of these devices may be connected to the bus. on power-up of these devices, all switches are in the off con- dition, and the internal registers contain all zeros. low power consumption and operating supply range of 2.7 v to 5.5 v make this part ideal for many applications. these parts may also be supplied from a dual 2.5 v supply. the adg714 and adg715 are available in a small 24-lead tssop package. product highlights 1. 2- or 3-wire serial interface 2. single/dual supply operation. the adg714 and adg715 are fully speci?ed and guaranteed with 3 v, 5 v, and 2.5 v supply rails. 3. low on resistance, typically 2.5 4. low leakage 5. power-on reset 6. small 24-lead tssop package spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation. i 2 c is a trademark of philips corporation. c 2013 781/461-3113 document feedback
C2C rev. adg714/adg715Cspecifications 1 (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v unless otherwise noted.) b version C40 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )2.5 typ v s = 0 v to v dd , i s = 10 ma 4.5 5 max on resistance match between channels ( r on )0.4 typ 0.8 max v s = 0 v to v dd , i s = 10 ma on resistance flatness (r flat(on) )0.6 typ v s = 0 v to v dd , i s = 10 ma 1.2 max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v 0.1 0.3 na max drain off leakage i d (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v 0.1 0.3 na max channel on leakage i d , i s (on) 0.01 na typ v d = v s = 1 v, or 4.5 v 0.1 0.3 na max digital inputs (sclk, din, sync , a0, a1) input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 3 pf typ digital output adg714 dout 2 output low voltage 0.4 v max i sink = 6 ma c out digital output capacitance 4 pf typ digital inputs (scl, sda) 2 input high voltage, v inh 0.7 v dd v min v dd + 0.3 v max input low voltage, v inl C0.3 v min 0.3 v dd v max i in , input leakage current 0.005 a typ v in = 0 v to v dd 1 a max v hyst , input hysteresis 0.05 v dd v min c in , input capacitance 6 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on adg714 20 ns typ v s = 3 v, r l = 300 , c l = 35 pf 32 ns max t on adg715 95 ns typ v s = 3 v, r l = 300 , c l = 35 pf 140 ns max t off adg714 8 ns typ v s = 3 v, r l = 300 , c l = 35 pf 15 ns max t off adg715 85 ns typ v s = 3 v, r l = 300 , c l = 35 pf 130 ns max break-before-make time delay, t d 8 ns typ v s = 3 v, r l = 300 , c l = 35 pf 1 ns min charge injection 3 pc typ v s = 2 v, r s = 0 , c l = 1 nf off isolation C60 db typ r l = 50 , c l = 5 pf, f = 10 mhz C80 db typ r l = 50 , c l = 5 pf, f = 1 mhz channel-to-channel crosstalk C70 db typ r l = 50 , c l = 5 pf, f = 10 mhz C90 db typ r l = 50 , c l = 5 pf, f = 1 mhz C3 db bandwidth 155 mhz typ r l = 50 , c l = 5 pf c s (off) 11 pf typ c d (off) 11 pf typ c d , c s (on) 22 pf typ power requirements v dd = 5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v 20 a max notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 guaranteed by design, not subject to production test. speci?cations subject to change without notice. c
C3C adg714/adg715 rev. specifications 1 (v dd = 3 v 10%, v ss = 0 v, gnd = 0 v unless otherwise noted.) b version C40 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )6 typ v s = 0 v to v dd , i s = 10 ma 11 12 max on resistance match between channels ( r on ) 0.4 typ v s = 0 v to v dd , i s = 10 ma 1.2 max on resistance flatness (r flat(on) ) 3.5 typ v s = 0 v to v dd , i s = 10 ma leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v 0.1 0.3 na max drain off leakage i d (off) 0.01 na typ v s = 1 v/3 v, v d = 3 v/1 v 0.1 0.3 na max channel on leakage i d , i s (on) 0.01 na typ v s = v d = 1 v, or 3 v 0.1 0.3 na max digital inputs (sclk, din, sync , a0, a1) input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 3 pf typ digital output adg714 dout 2 output low voltage 0.4 v max i sink = 6 ma c out digital output capacitance 4 pf typ digital inputs (scl, sda) 2 input high voltage, v inh 0.7 v dd v min v dd + 0.3 v max input low voltage, v inl C0.3 v min 0.3 v dd v max i in , input leakage current 0.005 a typ v in = 0 v to v dd 1 a max v hyst , input hysteresis 0.05 v dd v min c in , input capacitance 6 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on adg714 35 ns typ v s = 2 v, r l = 300 , c l = 35 pf 65 ns max t on adg715 130 ns typ v s = 2 v, r l = 300 , c l = 35 pf 200 ns max t off adg714 11 ns typ v s = 2 v, r l = 300 , c l = 35 pf 20 ns max t off adg715 115 ns typ v s = 2 v, r l = 300 , c l = 35 pf 180 ns max break-before-make time delay, t d 8 ns typ v s = 2 v, r l = 300 , c l = 35 pf 1 ns min charge injection 2 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf off isolation C60 db typ r l = 50 , c l = 5 pf, f = 10 mhz C80 db typ r l = 50 , c l = 5 pf, f = 1 mhz channel-to-channel crosstalk C70 db typ r l = 50 , c l = 5 pf, f = 10 mhz C90 db typ r l = 50 , c l = 5 pf, f = 1 mhz C3 db bandwidth 155 mhz typ r l = 50 , c l = 5 pf c s (off) 11 pf typ c d (off) 11 pf typ c d , c s (on) 22 pf typ power requirements v dd = 3.3 v i dd 10 a typ digital inputs = 0 v or 3.3 v 20 a max notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 guaranteed by design, not subject to production test. speci?cations subject to change without notice. c
C4C rev. adg714/adg715Cspecifications 1 dual supply b version C40 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 2.5 typ v s = v ss to v dd , i ds = 10 ma 4.5 5 max on resistance match between channels ( r on ) 0.4 typ v s = v ss to v dd , i ds = 10 ma 0.8 max on resistance flatness (r flat(on) ) 0.6 typ v s = v ss to v dd , i ds = 10 ma 1 max leakage currents v dd = +2.75 v, v ss = C2.75 v source off leakage i s (off) 0.01 na typ v s = +2.25 v/C1.25 v, v d = C1.25 v/+2.25 v 0.1 0.3 na max drain off leakage i d (off) 0.01 na typ v s = +2.25 v/C1.25 v, v d = C1.25 v/+2.25 v 0.1 0.3 na max channel on leakage i d , i s (on) 0.01 na typ v s = v d = +2.25 v/C1.25 v 0.1 0.3 na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 3 pf typ digital output adg714 dout 2 output low voltage 0.4 v max i sink = 6 ma c out digital output capacitance 4 pf typ digital inputs (scl, sda) 2 input high voltage, v inh 0.7 v dd v min v dd + 0.3 v max input low voltage, v inl C0.3 v min 0.3 v dd v max i in , input leakage current 0.005 a typ v in = 0 v to v dd 1 a max v hyst , input hysteresis 0.05 v dd v min c in , input capacitance 6 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on adg714 20 ns typ v s = 1.5 v, r l = 300 , c l = 35 pf 32 ns max t on adg715 133 ns typ v s = 1.5 v, r l = 300 , c l = 35 pf 200 ns max t off adg714 8 ns typ v s = 1.5 v, r l = 300 , c l = 35 pf 18 ns max t off adg715 124 ns typ v s = 1.5 v, r l = 300 , c l = 35 pf 190 ns max break-before-make time delay, t d 8 ns typ v s = 1.5 v, r l = 300 , c l = 35 pf 1 ns min charge injection 3 pc typ v s = 0 v, r s = 0 , c l = 1 nf off isolation C60 db typ r l = 50 , c l = 5 pf, f = 10 mhz C80 db typ r l = 50 , c l = 5 pf, f = 1 mhz channel-to-channel crosstalk C70 db typ r l = 50 , c l = 5 pf, f = 10 mhz C90 db typ r l = 50 , c l = 5 pf, f = 1 mhz C3 db bandwidth 155 mhz typ r l = 50 , c l = 5 pf c s (off) 11 pf typ c d (off) 11 pf typ c d , c s (on) 22 pf typ power requirements v dd = +2.75 v, v ss = C2.75 v i dd 15 a typ digital inputs = 0 v or 25 a max i ss 15 a typ 25 a max notes 1 temperature range is as follows: b version: C40 c to +85 c. 2 guaranteed by design, not subject to production test. speci?cations subject to change without notice. c (v dd = +2.5 v 10%, v ss = ?2.5 v 10%, gnd = 0 v unless otherwise noted.) v dd
adg714/adg715 C5C rev. adg714 timing characteristics 1, 2 parameter limit at t min , t max unit conditions/comments f sclk 30 mhz max sclk cycle frequency t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 0 ns min sync to sclk rising edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 33 ns min minimum sync high time t 9 3 20 ns max sclk rising edge to dout valid notes 1 see figure 1. 2 all input signals are speci?ed with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 c l = 20 pf, r l = 1 k . speci?cations subject to change without notice. sclk sync din dout t 8 t 4 t 6 t 5 t 2 t 3 t 1 t 7 t 9 db0 db7 db7 * db6 * db2 * db1 * db0 * * data from previous write cycle figure 1. 3-wire serial interface timing diagram (v dd = 2.7 v to 5.5 v. all speci?cations C40 c to +85 c unless otherwise noted.) c
adg714/adg715 C6C rev. adg715 timing characteristics 1 parameter limit at t min , t max unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd, sta , start/repeated start condition hold time t 5 100 ns min t su, dat , data setup time t 6 2 0.9 s max t hd, dat , data hold time 0 s min t 7 0.6 s min t su, sta , setup time for repeated start t 8 0.6 s min t su, sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop condition and a start condition t 10 300 ns max t r , rise time of both scl and sda when receiving 20 + 0.1c b 3 ns min t 11 250 ns max t f , fall time of sda when receiving t 11 300 ns max t f , fall time of sda when transmitting 0.1c b 3 ns min c b 400 pf max capacitive load for each bus line t sp 4 50 ns max pulsewidth of spike suppressed notes 1 see figure 2. 2 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the unde?ned region of scls falling edge. 3 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd . 4 input ?ltering on both the scl and sda inputs suppress noise spikes that are less than 50 ns. speci?cations subject to change without notice. sda scl start condition repeated start condition stop condition t 8 t 1 t 7 t 4 t 5 t 11 t 2 t 6 t 10 t 3 t 4 t 9 figure 2. 2-wire serial interface timing diagram (v dd = 2.7 v to 5.5 v. all speci?cations C40 c to +85 c unless otherwise noted.) c
adg714/adg715 C7C rev. absolute maximum ratings 1 (t a = 25 c unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C3.5 v analog inputs 2 . . . . . . . . . . . . . . . . . v ss C0.3 v to v dd +0.3 v or 30 ma, whichever occurs first digital inputs 2 . . . . . . . . . . . . . . . . . . . . C0.3 v to v dd +0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c tssop package ja thermal impedance . . . . . . . . . . . . . . . . . . . . 128 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . . 42 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 300 c infrared reflow (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 235 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. pin configurations 24-lead tssop top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 sync reset dout v ss s8 d8 s7 d7 s6 d6 s5 d5 sclk v dd din gnd s1 d1 s2 d2 s3 d3 s4 d4 adg714 top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 a0 reset a1 v ss s8 d8 s7 d7 s6 d6 s5 d5 scl v dd sda gnd s1 d1 s2 d2 s3 d3 s4 d4 adg715 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg714/adg715 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device c
adg714/adg715 C8C rev. adg714 pin function descriptions pin no. mnemonic description 1 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. these devices can accommodate serial input rates of up to 30 mhz. 2v dd positive analog supply voltage. 3 din serial data input. data is clocked into the 8-bit input register on the falling edge of the serial clock input. 4 gnd ground reference 5, 7, 9, 11, 14, sx source. may be an input or output. 16, 18, 20 6, 8, 10, 12, 13, dx drain. may be an input or output. 15, 17, 19 21 v ss negative analog supply voltage. for single supply operation this should be tied to gnd. 22 dout serial data output. this allows a number a parts to be daisy chained. data is clocked out of the input shift register on the rising edge of sclk. dout is an open-drain output that should be pulled to the supply with an external pull-up resistor. 23 reset active low control input. clears the input register and turns all switches to the off condition. 24 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and the input shift register is enabled. data is transferred on the falling edges of the following clocks. taking sync high updates the switches. adg715 pin function descriptions pin no. mnemonic description 1 scl serial clock line. this is used in conjunction with the sda line to clock data into the 8-bit input shift register. clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface. 2v dd positive analog supply voltage 3 sda serial data line. this is used in conjunction with the scl line to clock data into the 8-bit input shift register during the write cycle and used to readback one byte of data during the read cycle. it is a bidirectional open-drain data line which should be pulled to the supply with an external pull- up resistor. 4 gnd ground reference 5, 7, 9, 11, 14, sx source. may be an input or output. 16, 18, 20 6, 8, 10, 12, 13, dx drain. may be an input or output. 15, 17, 19 21 v ss negative analog supply voltage. for single supply operation this should be tied to gnd. 22 a1 address input. sets the second least signi?cant bit of the 7-bit slave address. 23 reset active low control input. clears the input reg ister and turns all switches to the off condition. 24 a0 address input. sets the least signi?cant bit of the 7-bit slave address. c
adg714/adg715 C9C rev. v dd most positive power supply potential. v ss most negative power supply in a dual supply application. in single supply applications, this should be tied to ground. i dd positive supply current i ss negative supply current gnd ground (0 v) reference s source terminal. may be an input or output. d drain terminal. may be an input or output. r on ohmic resistance between d and s r on on resistance match between any two channels, i.e., r on maxCr on min. r flat(on) flatness is de?ned as the difference between the maximum and minimum value of on resistance as measured over the speci?ed analog si gnal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d and s c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d , c s (on) on switch capacitance. measured with ref- erence to ground. c in digital input capacitance t on delay time between loading new data to the shift register and selected switches switching on. t off delay time between loading new data to the shift register and selected switches switching off. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by C3 dbs. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. insertion loss = 20 log 10 (v out with switch/ v out without switch. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current terminology c
adg714/adg715 C10C rev. Ctypical performance characteristics v d , v s , drain or source voltage C v 8 0 12345 t a = 25 c v ss = gnd 7 6 5 4 3 2 1 0 on resistance C v dd = 2.7v v dd = 3.3v v dd = 4.5v v dd = 5.5v tpc 1. on resistance as a function of v d (v s ) single supply v d or v s drain or source voltage C v on resistance C C2.7 C2.1 C1.5 C0.9 C0.3 0.3 0.9 1.5 2.1 2.7 8 7 6 5 4 3 2 1 v dd = +2.75v v ss = C2.75v v dd = +2.5v v ss = C2.5v v dd = +2.25v v ss = C2.25v t a = 25 c tpc 2. on resistance as a function of v d (v s ); dual supply v d or v s drain or source voltage C v 0 v dd = 5v v ss = gnd 0 on resistance C +25 c 12 3 5 4 8 7 6 5 4 3 2 1 +85 c C40 c tpc 3. on resistance as a function of v d (v s ) for different temperatures; v dd = 5 v v d or v s drain or source voltage C v 0 on resistance C 0.5 1.0 1.5 2.5 2.0 8 7 6 5 4 1 0 3.0 2 3 +25 c +85 c C40 c v dd = 3v v ss = gnd tpc 4. on resistance as a function of v d (v s ) for different temperatures; v dd = 3 v v d or v s drain or source voltage C v 7 6 5 4 3 2 1 0 on resistance C C2.5 C2.0 C1.5 C1.0 1.0 1.5 2.0 2.5 0.5 0 v dd = +2.5v v ss = C2.5v +85 c +25 c C40 c 8 C0.5 tpc 5. on resistance as a function of v d (v s ) for different temperatures; dual supply v d or v s C volts 0 current C na 012 4 3 v dd = 5v v ss = gnd t a = 25 c 5 0.04 0.02 C0.02 C0.04 i s , i d (on) i d (off) i s (off) tpc 6. leakage currents as a function of v d (v s ) c
adg714/adg715 C11C rev. voltage C v 0 current C na 0 1.0 0.5 2.0 1.5 v dd = 3v v ss = gnd t a = 25 c 3.0 0.04 0.02 C0.02 C0.04 i d (off) i s (off) i s , i d (on) 2.5 tpc 7. leakage currents as a function of v d (v s ) voltage C v 0 current C na C2 C1 0 i d (off) i s (off) i s , i d (on) 0.04 0.02 C0.02 C0.04 2 1 v dd = +2.5v v ss = C2.5v t a = 25 c tpc 8. leakage currents as a function of v d (v s ) dual supply temperature C c 0 current C na 10 20 30 70 40 0.1 0.05 C0.05 C0.1 60 50 i s , i d (on) i d (off) i s (off) v dd = +2.75v v ss = C2.75v v d = +2.25v/C1.25v v s = C1.25v/+2.25v v dd = +5v v ss = gnd v d = 4.5v/1v v s = 1v/4.5v 80 tpc 9. leakage currents as function of temperature temperature C c 0 current C na 10 20 30 70 40 0.1 0.05 C0.05 C0.1 60 50 i d , i s (on) i s (off) i d (off) v dd = 3v v ss = gnd v d = 3v/1v v s = 1v/3v 80 tpc 10. leakage currents as a function of temperature frequency C hz 0 30k attenuation C db C120 C100 C80 C60 C40 C20 100k 1m 10m 100m v dd = 5v t a = 25 c tpc 11. off isolation vs. frequency frequency C hz C14 300m attenuation C db C12 C10 C8 C6 C4 0 C2 100m 10m 1m 100k 30k tpc 12. on response vs. frequency c
adg714/adg715 C12C rev. frequency C hz 30k attenuation C db C90 C80 C60 C40 100k 1m 10m 100m v dd = 5v t a = 25 c C100 C70 C50 tpc 13. crosstalk vs. frequency voltage C v C3 t a = 25 c 10 0 C20 q inj C pc v dd = +2.5v v ss = C2.5v v dd = +3.3v v ss = gnd C15 C10 C5 5 C2 C1 0 1 2 3 4 5 v dd = +5v v ss = gnd tpc 14. charge injection vs. source/drain voltage temperature C c time C ns 10 20 30 70 40 45 40 60 50 v ss = gnd 80 35 30 25 20 15 10 5 0 t on , v dd = 5v t off , v dd = 3v t off , v dd = 5v t on , v dd = 3v tpc 15. t on /t off times vs. temperature for adg714 general description the adg714 and adg715 are serially controlled, octal spst switches, controlled by either a 2- or 3-wire interface. each bit of the 8-bit serial word corresponds to one switch of the part. a logic 1 in the particular bit position turns on the switch, while a logic 0 turns the switch off. because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches on. when changing the switch conditions, a new 8-bit word is writ- ten to the input shift register. some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. to minimize glitches on the output of these switches, the part cleverly compares the state of switches from the previous write cycle. if the switch is already in the on condition, and is required to stay on, there will be minimal glitches on the output of the switch. power-on reset on power-up of the device, all switches will be in the off con- dition and the internal shift register is ?lled with zeros and will remain so until a valid write takes place. serial interface 3-wire serial interface the adg714 has a 3-wire serial interface ( sync , sclk, and din), that is compatible with spi, qspi, microwire interface standards and most dsps. figure 1 shows the tim- ing diagram of a typical write sequence. data is written to the 8-bit shift register via din under the con- trol of the sync and sclk signals. data may be written to the shift register in more or less than eight bits. in each case the shift register retains the last eight bits that were written. when sync goes low, the input shift register is enabled. data from din is clocked into the shift register on the falling edge of sclk. each bit of the 8-bit word corresponds to one of the eight switches. figure 3 shows the contents of the input shift register. data appears on the dout pin on the rising edge of sclk suitable for daisy chaining, delayed of course by eight bits. when all eight bits have been written into the shift register, the sync line is brought high again. the switches are updated with the new con?guration and the input shift register is disabled. with sync held high, the input shift register is disabled, so further data or noise on the din line will have no effect on the shift register. s8 s7 s6 s5 s4 s3 s2 s1 db7 (msb) db0 (lsb) data bits figure 3. input shift register contents serial interface 2-wire serial interface the adg715 is controlled via an i 2 c-compatible serial bus. this device is connected to the bus as a slave device (no clock is generated by the switch). the adg715 has a 7-bit slave address. the ?ve msbs are 10010 and the two lsbs are determined by the state of the a0 and a1 pins. c
adg714/adg715 C13C rev. a repeated write function gives the user flexibility to update the matrix switch a number of times after addressing the part only once. during the write cycle, each data byte will update the con- ?guration of the switches. for example, after the matrix switch has acknowledged its address byte, and received one data byte, the switches will update after the data byte; if another data byte is written to the matrix switch while it is still the addressed slave device, this data byte will also cause a switch con?guration update. repeat read of the matrix switch is also allowed. input shift register the input shift register is eight bits wide. figure 3 illustrates the contents of the input shift register. data is loaded into the device as an 8-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 2. the 8-bit word consists of eight data bits, each controlling one sw itch. msb (bit 7) is loaded ?rst. write operation when writing to the adg715, the user must begin with an address byte and r/ w bit, after which the switch will acknowledge that it is prepared to receive data by pulling sda low. this address byte is followed by the 8-bit word. the write operation for the switch is shown in the figure 4. read operation when reading data back from the adg715, the user must begin with an address byte and r/ w bit, after which the sw itch will acknowledge that it is prepared to transmit data by pulling sda low. the readback operation is a single byte that consists of the eight data bits in the input register. the read operation for the part is shown in figure 5. scl sda s8 s7 s6 s5 s4 s3 s2 s1 0 0 1 0 a0 r/w stop cond by master ack by adg715 start cond by master address byte data byte ack by adg715 a1 1 figure 4. adg715 write sequence scl sda s8 s7 s6 s5 s4 s3 s2 s1 0 0 1 0 a0 r/ w stop cond by master ack by adg715 start cond by master address byte data byte no ack by master a1 1 figure 5. adg715 readback sequence the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte that consists of the 7-bit slave address followed by a r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth c lock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master will read from the slave device. however, if the r/ w bit is low, the master will write to the slave device. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or writt en, a stop con- dition is established by the master. a stop condition is de?ned as a low-to-high transition on the sda line while scl is high. in write mode, the master will pull the sda line high during the tenth clock pulse to establish a stop condition. in read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master will then bring the sda line low before the tenth clock pulse and then high during the tenth clock pulse to estab- lish a stop condition. see figure 4 for a graphical explanation of the serial interface. c
adg714/adg715 C14C rev. sda scl sda scl sda scl sda scl a1 a0 a1 a0 a1 a0 a1 a0 adg715 adg715 adg715 adg715 sda scl v dd v dd v dd master r p r p v dd figure 6. multiple adg715s on one bus - sclk din dout adg714 sync to other serial devices sclk din sync sclk din dout adg714 sync sclk din dout adg714 sync v dd v dd v dd r r r figure 7. multiple adg714 devices in a daisy-chained con?guration applications multiple devices on one bus figure 6 shows four adg715 devices on the same serial bus. each has a different slave address since the state of their a0 and a1 pins is different. this allows each switch to be written to or read from independently. daisy-chaining multiple adg714s a number of adg714 switches may be daisy-chained simply by using the dout pin. figure 7 shows a typical implementation. the sync pin of all three parts in the example are tied together. when sync is brought low, the input shift registers of all parts are enabled, data is written to the parts via din, and clocked through the shift registers. when the transfer is com plete, sync is brought high and all switches are updated simulta- neously. f urther shift registers may be added in series. power supply sequencing when using cmos devices, care must be taken to ensure correct power-supply sequencing. incorrect power-supply sequ encing can result in the device being subjected to stresses beyond those maximum ratings listed in the data sheet. digital and analog i nputs should always be applied after power supplies and ground. in dual supply applications, if digital or analog inputs may be applied to the device prior to the v dd and v ss supplies, the addition of a schottky diode connected between v ss and gnd will ensure that the device powers on correctly. for single supply operation, v ss should be tied to gnd as close to the device as possible. decoding multiple adg714s using an adg739 the dual 4-channel adg739 multiplexer can be used to multiplex a single chip select line to provide chip selects for up to four c
adg714/adg715 C15C rev. devices on the spi bus. figure 8 illustrates the adg739 and mul- tiple adg714s in such a typical configuration. all devices receive the same serial clock and serial data, but only one device will receive the sync signal at any one time. the adg739 is a serially controlled device also. one bit programmable pin of the micro- controller is used to enable the adg739 via sync2 , while another bit programmable pin is used as the chip select for the other serial devices, sync1 . driving sync2 low enables changes to be made to the addressed serial devices. by bringing sync1 low, the selected serial device hanging from the spi bus will be enabled and data will be clocked into its shift register on the falling edges of sclk. the convenient design of the matrix switch allows for different combinations of the four serial devices to be ad dressed at any one time. if more devices need to be addressed via one chip select line, the adg738 is an 8- channel device and would allow further expansion of the chip select scheme. there may be some digital feedthrough from the digital input lines because sclk and din are permanently connected to each device. using a burst clock will minimize the effects of digital feedthrough on the analog channels. other spi device din sclk din sclk din sclk din sclk adg714 adg714 sclk din s1a s4a da 1/2 of adg739 sync s3a s2a from controller or dsp sync1 sync2 sync sync sync sync sclk din v dd other spi device r vdd r vdd r vdd r vdd figure 8. addressing multiple adg714s using an adg739 c
adg714/adg715 C16C rev. c outline dimensions figure 1. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg714bru-reel ?40c to +85c 24-lead tssop ru-24 adg714bru-reel7 ?40c to +85c 24-lead tssop ru-24 adg714bruz ?40c to +85c 24-lead tssop ru-24 adg714bruz-reel ?40c to +85c 24-lead tssop ru-24 adg714bruz-reel7 ?40c to +85c 24-lead tssop ru-24 adg715bru ?40c to +85c 24-lead tssop ru-24 adg715bru-reel ?40c to +85c 24-lead tssop ru-24 adg715bru-reel7 ?40c to +85c 24-lead tssop ru-24 ADG715BRUZ ?40c to +85c 24-lead tssop ru-24 ADG715BRUZ-reel ?40c to +85c 24-lead tssop ru-24 ADG715BRUZ-reel7 ?40c to +85c 24-lead tssop ru-24 1 z = rohs compliant part. revision history 1/13rev. b to rev. c changes to dual supply table summary and i dd test conditions/comments ..................................................................... 4 changes to ordering guide ........................................................... 16 11/02rev. a to rev. b edits to features ................................................................................ 1 edits to general description ........................................................... 1 edits to product highlights ............................................................. 1 edits to specifications ................................................................... 3, 4 edits to tpcs 2 and 5 ..................................................................... 10 edits to tpcs 8 and 9 ..................................................................... 11 edits to tpcs 14 .............................................................................. 12 edits to figure 8 ............................................................................... 15 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00043-0-1/13(c)

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